The invention relates to a semiconductor device. More specifically, the invention relates to a method for fabricating a dual poly gate in a semiconductor device having an improved gate profile.
Semiconductor devices, e.g., dynamic random access memories (DRAMs) include a cell region and a peripheral circuit region. In particular, complementary metal oxide semiconductor (CMOS) devices are arranged in the peripheral circuit region. A p-channel-type MOS (PMOS) transistor in general CMOS devices has a buried channel structure. The buried channel structure involves a reduction in channel length in more highly integrated semiconductor devices, thus causing an increase in leakage current when applying a high electrical field to the structure. Accordingly, a dual poly gate structure has been used to form a PMOS transistor having a surface channel structure. The dual poly gate structure has a p-type poly gate doped with p-type impurities arranged in a PMOS region, and an n-type poly gate doped with n-type impurities arranged in an NMOS region.
FIG. 1 is an SEM (scanning electron micrograph) illustrating conventional bridge defects.
Referring to FIG. 1, heat treatment activates impurities doped into a gate conductive layer when forming a dual poly gate. During the heat treatment, the gate conductive layer undergoes crystallization. For this reason, etching through the crystalline poly gate layer used to form a poly gate on a semiconductor substrate involves a significantly lower etching rate, as compared to an amorphous poly gate layer. As a result, there is an undesired variation in gate profiles, for example an unexpected increase in the width of the gate conductive layer. The variation in gate profile may cause “bridge” defects 100 where the gate conductive layer is in contact with a landing plug formed between gate stacks (see FIG. 1), thus resulting in the deterioration of device characteristics.